Standard Operation for Maskable Interrupts
3-12
Figure 3−4. Standard Operation for CPU Maskable Interrupts
Interrupt request sent to CPU
Set corresponding IFR flag bit.
Interrupt enabled by
INTM bit?
Clear corresponding IFR bit.
Yes
No
Clear corresponding IER bit.
Set INTM and DBGM. Clear LOOP,
EALLOW, and IDLESTAT.
Execute interrupt service routine.
Program continues
Increment and temporarily store PC.
Fetch interrupt vector.
Perform automatic context save.
Increment SP by 1.
Load PC with fetched vector.
Empty pipeline.
This sequence
protected from interrupts
Interrupt enabled in
IER?
Yes
No
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