Overview of Emulation Features
7-2
7.1 Overview of Emulation Features
The CPU’s hardware extensions for advanced emulation features provide
simple, inexpensive, and speed-independent access to the CPU for sophisti-
cated debugging and economical system development, without requiring the
costly cabling and access to processor pins required by traditional emulator
systems. It provides this access without intruding on system resources.
The on-chip development interface provides:
- Minimally intrusive access to internal and external memory
- Minimally intrusive access to CPU and peripheral registers
- Control of the execution of background code while continuing to service
time-critical interrupts
J Break on a software breakpoint instruction (instruction replacement)
J Break on a specified program or data access without requiring instruc-
tion replacement (accomplished using bus comparators)
J Break on external attention request from debug host or additional
hardware
J Break after the execution of a single instruction (single-stepping)
J Control over the execution of code from device power up
- Nonintrusive determination of device status
J Detection of a system reset, emulation/test-logic reset, or power-
down occurrence
J Detection of the absence of a system clock or memory-ready signal
J Determination of whether global interrupts are enabled
J Determination of why debug accesses might be blocked
- Rapid transfer of memory contents between the device and a host (data
logging)
- A cycle counter for performance benchmarking. With a 100-MHz cycle
clock, the counter can benchmark actions up to 3 hours in duration.
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