Reference Tables for C2xLP Code Migration Topics
D.5 Reference Tables for C2xLP Code Migration Topics
Table D−6 through Table D−10 explain the major differences between the
C2xLP and C28x architectures and in their respective code generation pro-
cess. These tables are organized to highlight the differences in interrupts, CPU
registers, memory maps, instructions, registers, and syntax. While migrating
the C2xLP code, check the tables for these key differences to make the neces-
sary changes to the source to avoid assembler or linker errors.
Table D−6. C2xLP and C28x Differences in Interrupts
Migration topic C2xLP C28x
1 Interrupt flag register IFR − Memory mapped register
Write 1 to clear bits set in IFR
IFR is a CPU register
Write 0 to clear bits set in IFR
2 Interrupt enable register IMR – Memory mapped register Renamed as IER and is a CPU regis-
ter
3 TRAP instruction Only one TRAP vector
TRAP
Affects:
INTM bit is not affected
multiple,32− TRAP vectors
TRAP 0, .. TRAP31
Affects:
INTM bit is set to 1
4 INTR instruction syntax INTR0
..
INTR31
Affects:
IFR not cleared
IMR not affected
INTM bit =1
INTR INT0
….
INTR INT31
Affects:
IFR cleared
IER affected
INTM bit =1
5 NMI Instruction NMI TRAP NMI
6 CLRC INTM instruction CLRC INTM instruction blocks
all interrupts until the next in-
struction is executed.
CLRC INTM
next_instn ;interrupts
;blocked
;until this
;executed
Interrupts enabled after the instruc-
tion
CLRC INTM
7 Interrupt enable and return
from interrupt service
CLRC INTM
RET
IRET
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