Data Logging
7-25Emulation Features
Table 7−4. Start Address and DMA Registers
Address Name Access Description
00 0838
16
ADDRL R/W
Start address register (lower 16 bits)
15:0 Lower 16 bits of start address
00 0839
16
ADDRH R/W
Word counter/start address register (upper 6 bits)
15:8 Word counter. When using this to stop the data
logging transfer, set the counter to 256 − n,
where n is the number of 32-bit words to
transfer. Otherwise set the counter to 0.
7:6 Reserved. Set to 0.
5:0 Upper 6 bits of start address
00 083E
16
DMA_CNTRL R/W
DMA control register
15:14 Set to 0
13 Set to 1
12 Set to 1
11 Give higher priority to:
0: CPU (nonpreemptive mode)
1: Data logging (preemptive mode)
10 Allow data logging during time-critical ISR?
0: No
1: Yes
9 Allow data logging while DBGM = 1?
0: No (polite accesses)
1: Yes (rude accesses)
8:6 Set to 1
5:4 0: EMU0/EMU1 using TCK
1: EMU0/EMU1 using FCK/2
2: JTAG signals
3: Reserved
3:2 Method for ending data logging session:
0: Use the count register to stop data logging
1: Use an end address to stop data logging
1:0 Data logging control/status:
0: Release resource from data logging operation
1: Claim resource for data logging operation
2: Enable resource for data logging operation
3: Data logging operation is complete. Bits 14:10
are corrupted when this occurs.
00 083F
16
DMA_ID R
DMA ID register
15:14 Resource control:
0: Resource is free
1: Application owns resource
2: Debugger owns resource
13:12 Set to 3.
11:0 Set to 1.
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