Execution Control Modes
7-11Emulation Features
Caution about breakpoints within time-critical interrupt service routines
Do not use breakpoints within time-critical interrupt service routines. They will
cause the device to enter the debug-halt state, just as if the breakpoint were
located in normal code. Once in the debug-halt state, the CPU services re-
quests for RS, NMI, and those interrupts enabled in the DBGIER and the IER.
After approving a maskable interrupt, the CPU disables the interrupt in the
IER. This prevents subsequent occurrences of the interrupt from being ser-
viced until the IER is restored by a return from interrupt (IRET) instruction or
until the interrupt is deliberately re-enabled in the interrupt service routine
(ISR). Do not reenable that interrupt’s IER bit while using breakpoints within
the ISR. If you do so and the interrupt is triggered again, the CPU performs
a new context save and restarts the interrupt service routine.
7.4.3 Summary of Stop Mode and Real-Time Mode
Figure 7−4 (page 7-12) is a graphical summary of the differences between the
execution states of stop mode and real-time mode. Table 7−3 (page 7-13) is
a summary of how interrupts are handled in each of the states of stop mode
and real-time mode.
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