DT-DMA Mechanism
7-16
7.6 DT-DMA Mechanism
The debug-and-test direct memory access (DT-DMA) mechanism provides
access to memory, CPU registers, and memory-mapped registers (such as
emulation registers and peripheral registers) without direct CPU intervention.
DT-DMAs intrude on CPU time; however, you can block them by setting the
debug enable mask bit (DBGM) in ST1.
Because the DT-DMA mechanism uses the same memory-access mecha-
nism as the CPU, any read or write access that the CPU can perform in a single
operation can be done by a DT-DMA. The DT-DMA mechanism presents an
address (and data, in the case of a write) to the CPU, which performs the op-
eration during an unused bus cycle (referred to as a hole). Once the CPU has
obtained the desired data, it is presented back to the DT-DMA mechanism.
The DT-DMA mechanism can operate in the following modes:
- Nonpreemptive mode.The DT-DMA mechanism waits for a hole on the
desired memory buses. During the hole, the DT-DMA mechanism uses
them to perform its read or write operation. These holes occur naturally
while the CPU is waiting for newly fetched instructions, such as during a
branch.
- Preemptive mode. In preemptive mode, the DT-DMA mechanism forces
the creation of a hole and performs the access.
Nonpreemptive accesses to zero-wait-state memory take no cycles away
from the CPU. If wait-stated memory is accessed, the pipeline stalls during
each wait state, just as a normal memory access would cause a stall. In real-
time mode, DT-DMAs to program memory cannot occur when application
code is being run from memory with more than one wait state.
DT-DMAs can be polite or rude.
- Polite accesses. Polite DT-DMAs require that DBGM = 0.
- Rude accesses. Rude DT-DMAs ignore DBGM.
Figure 7−5 summarizes the process for handling a request from the DT-DMA
mechanism.
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