Summary of Architecture Differences Between C2xLP and C28x
C.1 Summary of Architecture Differences Between C2xLP and C28x
The C28x CPU features many improvements over the C2xLP CPU. A summa-
ry of the enhancements is given here.
Table C−1. General Features
Feature C2xLP C28x
Program memory space 64K (16 address signals) 4M (22 address signals)
Data memory space 64K (16 address signals) 4G (32 address signals)
Number of internal buses 3 (prog, data-read, data-write) 3 (prog, data-read, data-write)
Addressable word size 16 16/32
Multiplier 16 bits 16/32 bits
Maskable CPU interrupts
6 14
C.1.1 Enhancements of the C28x over the C2xLP:
- Much higher MHz operation
- 32 x 32 MAC
- 16 x16 Dual MAC
- 32-bit register file
- 32-bit single-cycle operations
- 4M linear program-address reach
- 4G linear data-address reach
- Dedicated software stack pointer
- Monitorless real-time emulation
- 40−50% better C code efficiency than C2xLP
- 20−30% better assembly code efficiency than C2xLP
- Atomic operation eliminates need to disable/re-enable interrupts
- Extended debugging features (Analysis block, data logging, etc.)
- Faster interrupt context save/restore
- More efficient addressing modes
- Unified memory map
- Byte packing and unpacking operations
When you first recompile your C2xLP code set for C28x, you will not be able
to take advantage of every enhancement since you are limited by the original
source code. Once you begin migrating your code, however, you will quickly
begin to take advantage of the full capabilities the C28x offers. See
Appendix D for help with migration to C28x.
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