Nonmaskable Interrupts
3-17CPU Interrupts and Reset
3.5 Nonmaskable Interrupts
Nonmaskable interrupts cannot be blocked by any of the enable bits (the INTM
bit, the DBGM bit, and enable bits in the IFR, IER, or DBGIER). The C28x im-
mediately approves this type of interrupt and branches to the corresponding
interrupt service routine. There is one exception to this rule: When the CPU
is halted in stop mode (an emulation mode), no interrupts are serviced. Stop
mode is described in section 7.4.1 on page 7-7.
The C28x nonmaskable interrupts include:
- Software interrupts (the INTR and TRAP instructions).
- Hardware interrupt NMI
- Illegal-instruction trap
- Hardware reset interrupt (RS)
The software interrupt instructions and NMI
are described in this section. The
illegal-instruction trap and reset are described in sections 3.6 and 3.7, respec-
tively.
3.5.1 INTR Instruction
You can use the INTR instruction to initiate one of the following interrupts by
name: INT1−INT14, DLOGINT, RTOSINT and NMI. For example, you can
execute the interrupt service routine for INT1
by using the following instruction:
INTR INT1
Once an interrupt is initiated by the INTR instruction, how it is handled depends
on which interrupt is specified:
- INT1−INT14, DLOGINT, and RTOSINT. These maskable interrupts have
corresponding flag bits in the IFR. When a request for one of these inter-
rupts is received at an external pin, the corresponding IFR bit is set and
the interrupt must be enabled to be serviced. In contrast, when one of
these interrupts is initiated by the INTR instruction, the IFR flag is not set,
and the interrupt is serviced regardless of the value of any enable bits.
However, in other respects, the INTR instruction and the hardware request
are the same. For example, both clear the IFR bit that corresponds to the
requested interrupt. For more details, see section 3.4 on page 3-11.
- NMI. Because this interrupt is nonmaskable, a hardware request at a pin
and a software request with the INTR instruction lead to the same events.
These events are identical to those that take place during a TRAP instruc-
tion (see section 3.5.2).
Chapter 6, C28x Assembly Language Instructions, contains a detailed de-
scription of the INTR instruction.
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