Program Flow
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2.5.4 Instruction Pipeline
Each instruction passes through eight independent phases that form an
instruction pipeline. At any given time, up to eight instructions may be active,
each in a different phase of completion. Not all reads and writes happen in the
same phases, but a pipeline-protection mechanism stalls instructions as
needed to ensure that reads and writes to the same location happen in the or-
der in which they are programmed.
To maximize pipeline efficiency, an instruction-fetch mechanism attempts to
keep the pipeline full. Its role is to fill an instruction-fetch queue, which holds
instructions in preparation for decoding and execution. The instruction-fetch
mechanism fetches 32-bits at a time from program memory; it fetches one
32-bit instruction or two 16-bit instructions.
The instruction-fetch mechanism uses three program-address counters: the
program counter (PC), the instruction counter (IC), and the fetch counter (FC).
When the pipeline is full the PC will always point to the instruction in its
decode 2 pipeline phase. The IC points to the next instruction to be processed.
When the PC points to a 1-word instruction, IC = (PC+1); when the PC points
to a 2-word instruction, IC = (PC+2). The value in the FC is the address from
which the next fetch is to be made.
The pipeline and the instruction-fetch mechanism are described in more detail
in Chapter 4, Pipeline.
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