Architecture Changes
Table F−2. ST1 Register Bits
Bit(s) Syntax Description Reset Value R/W
0 INTM Interrupt Enable Mask Bit 1 (disabled) R/W
1 DBGM DeBug Enable Mask Bit 1 (disabled) R/W
2 PAGE0 PAGE0 Direct/Stack Address Mode 0 R/W
3 VMAP Vector Map Bit VMAP input R/W
4 SPA Stack Pointer Align Bit 0 R/W
5 LOOP Loop Instruction Status Bit 0 R
6 EALLOW Emulation Access Enable Bit 0 R/W
7 IDLESTAT IDLE Status Flag Bit 0 R
8 AMODE Address Mode Bit 0 R/W
9 OBJMODE Object Compatibility Mode Bit 0 R/W
10 RESERVED Reserved for future use 0 R
11 M0M1MAP M0 and M1 Mapping Mode Bit 1 R
12 XF XF Status Bit 0 R/W
15:13
ARP Auxiliary Register Pointer 0 R/W
AMODE: This mode selects the appropriate addressing mode decodes for compatibility with the
C2xLP device. For all C27x/C28x based projects leave this bit as 0.
OBJMODE: This mode is used to select between C27x object mode (OBJMODE == 0) and C28x
object mode (OBJMODE == 1) compatibility. This bit is set by the ”C28OBJ” (or ”SETC
OBJMODE”) instructions. This bit is cleared by the ”C27OBJ” (or ”CLRC OBJMODE”)
instructions. The pipeline is flushed when setting or clearing this bit using the given
instructions. This bit can be saved and restored by interrupts and when restoring the ST1
register. This bit is set to 0 on reset.
M0M1MAP: This mode is used to remap block M0 and M1 in program memory space as discussed
in detail in section F.1.2. This bit is set by the ”C28MAP” (or ”SETC M0M1MAP”)
instructions. This bit is cleared by the ”C27MAP” (or ”CLRC M0M1MAP”) instructions.
The pipeline is flushed when setting or clearing this bit using the given instructions. This
bit cannot be restored by interrupts and when restoring the ST1 register (read only).
XF: This bit reflects the current state of the XFS output signal. This signal is for C2xLP
compatibility and is not used by C27x users.
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