3-1
CPU Interrupts and Reset
This chapter describes the available CPU interrupts and how they are handled
by the CPU. It also explains how to control those interrupts that can be con-
trolled through software. Finally, it describes how a hardware reset affects the
CPU.
Topic Page
3.1 CPU Interrupts Overview 3-2. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
3.2 CPU Interrupt Vectors and Priorities 3-4. . . . . . . . . . . . . . . . . . . . . . . . . . . .
3.3 Maskable Interrupts: INT1
−INT14, DLOGINT, and RTOSINT 3-6. . . . . . .
3.4 Standard Operation for Maskable Interrupts 3-11. . . . . . . . . . . . . . . . . . . .
3.5 Nonmaskable Interrupts 3-17. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
3.6 Illegal-Instruction Trap 3-22. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
3.7 Hardware Reset (RS
) 3-23. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Chapter 3
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