Execution Control Modes
7-9Emulation Features
7.4.2 Real-Time Mode
Real-time mode provides for the debugging of code that interacts with inter-
rupts that must not be disabled. Real-time mode allows you to suspend back-
ground code at break events while continuing to execute time-critical interrupt
service routines (also referred to as foreground code). In real-time mode, the
CPU can operate in the following execution states:
- Debug-halt state. This state is entered through a break event such as the
decoding of a software breakpoint instruction or the occurrence of an anal-
ysis breakpoint/watchpoint. This state can also be enter by a request from
the host processor. You can place the device into one of the other two
states by giving the appropriate command to the debugger.
In this state, only time-critical interrupts can be serviced. No other code can
be executed. Maskable interrupts are considered time-critical if they are en-
abled in the debug interrupt enable register (DBGIER). If they are also en-
abled in the interrupt enable register (IER), they are serviced. The interrupt
global mask bit (INTM) is ignored. NMI and RS are also considered time-criti-
cal, and are always serviced once requested. It is possible for multiple inter-
rupts to occur and be serviced while the device is in the debug-halt state.
Suspending execution adds only one cycle to interrupt latency. When the
C28x returns from a time-critical ISR, it reenters the debug-halt state.
If a CPU reset occurs (initiated by RS), the device runs the corresponding
interrupt service routine until that routine clears the debug enable mask bit
(DBGM) in status register ST1. When a reset occurs, DBGM is set, disab-
ling debug events. To reenable debug events, the interrupt service routine
must clear DBGM. Only then will the outstanding emulation-suspend con-
dition be recognized.
Note:
Should a time-critical interrupt occur in real-time mode at the precise mo-
ment that the debugger receives a RUN command, the time-critical interrupt
will be taken and serviced in its entirety before the CPU changes states.
- Single-instruction state. This state is entered when you you tell the de-
bugger to execute a single instruction by using a RUN 1 command or a
STEP 1 command. The CPU executes the single instruction pointed to by
the PC and then returns to the debug-halt state (it executes from one inter-
rupt boundary to the next).
If an interrupt occurs in this state, the command used to enter this state deter-
mines whether that interrupt can be serviced. If a RUN 1 command was
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