Reset Values of and Instructions for Accessing the Registers
A.1 Reset Values of and Instructions for Accessing the Registers
Table A−1 lists the CPU status and control registers, their reset values, and the
instructions that are available for accessing the registers.
Table A−1. Reset Values of the Status and Control Registers
Register Description Reset Value Instructions
ST0 Status register 0 0000 0000 0000 0000
2
PUSH, POP, SETC, CLRC
ST1 Status register 1 0000 M0000000V011
2
PUSH, POP, SETC, CLRC
IFR Interrupt flag register 0000 000000000000
2
PUSH, AND, OR
IER Interrupt enable register 0000 0000 0000 0000
2
MOV, AND, OR
DBGIER
Debug interrupt enable register 0000000000000000
2
PUSH, POP
Note: V: Bit 3 of ST1 (the VMAP bit) depends on the level of the VMAP input signal at reset. If the VMAP signal is low, the
VMAP bit is 0 after reset; if the VMAP signal is high, the VMAP bit is 1 after reset. For C28x devices that do not pin out
VMAP, the signal is tied high internal to the device.
M: Bit 11 of ST1 (the M0M1MAP bit) depends on the level of the M0M1MAP input signal at reset. If the M0M1MAP
signal is low, the bit is 0, high bit is 1. For C28x devices that do not pinout MOM1MAP, the signal is tied high internal to
the device.
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