CPU Registers
2-13Central Processing Unit
Modes, on page 5-10 . The auxiliary registers are: XAR0, XAR1, XAR2, XAR3,
XAR4, XAR5, XAR6, and XAR7.
Many instructions allow you to access the 16 LSBs of XAR0−XAR7. As shown
in Figure 2−8, the 16 LSBs of the auxiliary registers are referred to as
AR0−AR7. AR0−AR7 can be used as general purpose registers for loop con-
trol and for efficient 16-bit comparisons.
When accessing AR0−AR7, the upper 16 bits of the register (known as AR0H−
AR7H) may or may not be modified, depending on the instruction used (see
Chapter 6 for information on the behavior of particular instructions). AR0H−
AR7H are accessed only as part of XAR0−XAR7 and are not individually ac-
cessible.
Figure 2−8. XAR0 − XAR7 Registers
XARn(31:0)
ARnH = XARn(31:16)
ARn = XARn(15:0)
n = number 0 through 7
For ACC operations, all 32 bits are valid (@XARn). For 16-bit operations, the
lower 16 bits are used and upper 16 bits are ignored (@ARn).
XAR0 − XAR7 can also be used by some instructions to point to any value in
program memory; see Section 5.6, Indirect Addressing Modes.
Many instructions allow you to access the 16 least significant bits (LSBs) of
XAR0
−XAR7. As shown in Figure 2−9, 16 LSBs of XAR0−XAR7 are known
as one auxiliary register of AR0
−AR7.
Figure 2−9. XAR0 − XAR7
XAR0(32:0)
AR0 = XAR0(15:0)
XAR7(32:0)
AR7 = XAR7(15:0)
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