Status Register (ST0)
2-21Central Processing Unit
V
Bit 6
Overflow flag. If the result of an operation causes an overflow in the register holding the
result, V is set and latched. If no overflow occurs, V is not modified. Once V is latched, it
remains set until it is cleared by reset or by a conditional branch instruction that tests V.
Such a conditional branch clears V regardless of whether the tested condition (V = 0 or
V = 1) is true.
An overflow occurs in ACC (and V is set) if the result of an addition or subtraction does not
fit within the signed numerical range −2
31
to (+2
31
− 1), or 80000000
16
to 7FFFFFFF
16
.
An overflow occurs in AH, AL, or another 16-bit register or data-memory location if the result
of an addition or subtraction does not fit within the signed numerical range −2
15
to (+2
15
−
1), or 8000
16
to 7FFF
16
.
The instructions CMP, CMPB and CMPL do not affect the state of the V flag. Table 2−6 lists
the instructions that are affected by V flag. See Chapter 6 for more details on instructions.
V can be summarized as follows:
0
V has been cleared.
1 An overflow has been detected, or V has been set.
Table 2−6. Instructions Affected by V flag
Instruction Description
ABS ACC if(ACC == 0x8000 0000) V = 1
ABSTC ACC if(ACC == 0x8000 0000) V = 1
ADD ACC,#16bit << shift V = 1 on signed overflow
ADD ACC,loc16 << shift V = 1 on signed overflow
ADD ACC,loc16 << T V = 1 on signed overflow
ADD AX,loc16 V = 1 on signed overflow
ADD loc16,#16bitSigned V = 1 on signed overflow
ADD loc16,AX V = 1 on signed overflow
ADDB ACC,#8bit V = 1 on signed overflow
ADDB AX,#8bitSigned V = 1 on signed overflow
ADDCL ACC,loc32 V = 1 on signed overflow
ADDCU ACC,loc16 V = 1 on signed overflow
ADDL ACC,loc32 V = 1 on signed overflow
ADDL loc32,ACC V = 1 on signed overflow
ADDU ACC,loc16 V = 1 on signed overflow
ADDUL ACC,loc32 V = 1 on signed overflow
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