Code Examples
Table D−3. Code to Enable an Interrupt
C2xLP C28x
SETC INTM
LDP #0
LACL IMR
OR #INTx
SACL IMR
CLRC INTM
OR IER,#INTx
;operation is atomic and
;will not be interrupted.
Table D−4. Code to Clear the IFR Register
C2xLP C28x
;write 1 to clear
SETC INTM
LDP #0
SPLK #0FFFFh,IFR
CLRC INTM
;write 0 to clear
AND IFR,#~INTx
;operation is atomic and
;will not be interrupted
D.4.3 Context Save/Restore
The C28x automatically saves a number of registers on each interrupt. To per-
form a full context save, some additional code must be added. Table D−5
shows a typical full context save and restore for both processors.
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