Pipeline Protection
4-13Pipeline
Example 4−4. Conflict Between a Read From and a Write to Same Memory Location
I1: MOV @VarA,AL ; Write AL to data−memory location
I2: MOV AH,@VarA ; Read same location, store value in AH
DZ Kl RZ E W Cycle
I1 1
I2 I1 2
I2 I1 3
I2 I1 4
I2 I1 5
I2 6
I2 7
I2 8
You can reduce or eliminate these types of pipeline-protection cycles if you can
take other instructions in your program and insert them between the instruc-
tions that conflict. Of course, the inserted instructions must not cause conflicts
of their own or cause improper execution of the instructions that follow them.
For example, the code in Example 4−4 could be improved by moving a CLRC
instruction to the position between the MOV instructions (assume that the
instructions following CLRC SXM operate correctly with SXM = 0):
I1: MOV @VarA,AL ; Write AL to data−memory location
CLRC SXM ; SXM = 0 (sign extension off)
I2: MOV AH,@VarA ; Read same location, store value in AH
Inserting the CLRC instruction between I1 and I2 reduces the number of pipe-
line-protection cycles to two. Inserting two more instructions would remove the
need for pipeline protection. As a general rule, if a read operation occurs within
three instructions from a write operation to the same memory location, the
pipeline protection mechanism adds at least one inactive cycle.
4.4.2 Protection Against Register Conflicts
All reads from and writes to CPU registers occur in either the D2 phase or the
E phase of an instruction. A register conflict arises when an instruction
attempts to read and/or modify the content of a register (in the D2 phase)
before a previous instruction has written to that register (in the E phase).
The pipeline-protection mechanism resolves register conflicts by holding the
later instruction in its D2 phase for as many cycles as needed (one to three).
You do not have to consider register conflicts unless you wish to achieve
maximum pipeline efficiency. If you choose to reduce the number of pipe-
line-protection cycles, you can identify the pipeline phases in which registers
are accessed and try to move conflicting instructions away from each other.
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