Visualizing Pipeline Activity
4-7Pipeline
4.2 Visualizing Pipeline Activity
Consider Example 4−2, which lists eight instructions, I1−I8, and shows a
diagram of the pipeline activity for those instructions. The F1 column shows
addresses and the F2 column shows the instruction opcodes read at those
addresses. During an instruction fetch, 32 bits are read, 16 bits from the speci-
fied address and 16 bits from the following address. The D1 column shows
instructions being isolated in the instruction-fetch queue, and the D2 column
indicates address generation and modification of address registers. The
Instruction column shows the instructions that have reached the D2 phase.
The R1 column shows addresses, and the R2 column shows the data values
being read from those addresses. In the E column, the diagram shows results
being written to the low half of the accumulator (AL). In the W column, address
and a data values are driven simultaneously on the appropriate memory
buses. For example, in the last active W phase of the diagram, the address
000205
16
is driven on the data-write address bus (DWAB), and the data value
1234
16
is driven on the data-write data bus (DWDB).
The highlighted blocks in Example 4−2 indicate the path taken by the instruc-
tion ADD AL,*AR0++. That path can be summarized as follows:
Phase Activity Shown
F1 Drive address 000042
16
on the program address bus (PAB).
F2 Read the opcodes F347 and F348 from addresses 000042
16
and
000043
16
, respectively.
D1 Isolate F348 in the instruction-fetch queue.
D2 Use XAR0 = 0066
16
to generate source address 00000066
16
and then
increment XAR0 to 0067
16
.
R1 Drive address 000066
16
on the data-read data bus (DRDB).
R2 Read the data value 1 from address 0000 0066
16
.
E Add 1 to content of AL (1230
16
) and store result (1231
16
) to AL.
W
No activity
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