Data Logging
7-23Emulation Features
7.8 Data Logging
Data logging enables the C28x to send selected memory values to a host proc-
essor using the standard JTAG port and an XDS510 or other compatible scan
controller. You control data logging activity with your application code.
To perform data logging, you must create a linear buffer of 32-bit words to hold
a packet of information. Your application code controls the size, format, and
location of this buffer and also determines when to send a buffer’s contents
to the host. You can control the size of a data logging buffer in two ways:
- Specify a count value in the upper eight bits of ADDRH (when the number
of 32-bit words you want to log is between 1 and 256)
- Specify an end address
Note:
When the debugger is not active, the data logging transfers are considered
complete as soon as they are enabled to prevent the application software
from getting stuck when there is nothing to receive the data.
7.8.1 Creating a Data Logging Transfer Buffer
To create a data logging transfer buffer, follow these steps in your application
code:
1) Execute the EALLOW instruction to enable access to emulation registers.
2) Specify the start address of the buffer in ADDRL and the six LSBs of
ADDRH (see Figure 7−6 and Figure 7−7). The address in ADDRL and
ADDRH is called the transfer address.
3) Use either of the following methods to specify when data logging is to end:
a) If the number of words you want to log is between 1 and 256, specify
a count value in the upper eight bits of ADDRH (see Figure 7−7). The
form of the count value is 256−n, where n is the number of 32-bit words
you want to log. As each word is transferred, both the transfer address
and the count value are decremented.
b) If the number of words you want to log is greater than 256, specify a
data logging end address in REFL and the six LSBs of REFH (see
Figure 7−8 and Figure 7−9). Load the ten MSBs of REFH with 0s.
When using this method, be sure to set the data logging end address
control register (EVT_CNTRL) first, and then the DMA control register
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