Architecture Changes
Figure F−3. Code for a Full Context Save/Restore for C28x vs C27x
C28x Full Context Save/Restore
−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−
IntX: ; 8 cycles
PUSH AR1H:AR0H ; 32−bit
PUSH XAR2 ; 32−bit
PUSH XAR3 ; 32−bit
PUSH XAR4 ; 32−bit
PUSH XAR5 ; 32−bit
PUSH XAR6 ; 32−bit
PUSH XAR7 ; 32−bit
PUSH XT ; 32−bit
; + 8 = 16 cycles
.
.
.
POP XT
POP XAR7
POP XAR6
POP XAR5
POP XAR4
POP XAR3
POP XAR2
POP AR1H:AR0H
IRET
; 16 cycles
C27X Full Context Save/Rest
−−−−−−−−−−−−−−−−−−−−−−−−−−−−
IntX: ; 8 cycles
push AR3:AR2
push AR5:AR4
push XAR6
push XAR7
; + 4 = 12 cycles
.
.
.
pop XAR7
pop XAR6
pop AR5:AR4
pop AR3:AR2
iret
; 12 cycles
If you perform a task-switch operation (stack changes), the RPC register must
be manually saved. You are not to save the RPC register if the stack is not
changed.
F.1.3 B0/B1 Memory Map Consideration
Another architecture change to consider is the C27x mapping of blocks B0 and
B1. To avoid confusion, on the C28x these blocks are known as M1 and M0
respectively. On the C27x, block B1 was mapped to only data space and block
B0 was mapped both in program and data space. In addition, block B0 was
mapped to different address ranges in program and in data space. The C27x
mapping of these blocks is shown in Figure F−4.
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