Freezes in Pipeline Activity
4-10
4.3 Freezes in Pipeline Activity
This section describes the two causes for freezes in pipeline activity:
- Wait states
- An instruction-not-available condition
4.3.1 Wait States
When the CPU requests a read from or write to a memory device or peripheral
device, that device may take more time to finish the data transfer than the CPU
allots by default. Each device must use one of the CPU ready signals to insert
wait states into the data transfer when it needs more time. The CPU has three
independent sets of ready signals: one set for reads from and writes to pro-
gram space, a second set for reads from data space, and a third set for writes
to data space. Wait-state requests freeze a portion of the pipeline if they are
received during the F1, R1, or W phase of an instruction:
- Wait states in the F1 phase. The instruction-fetch mechanism halts until
the wait states are completed. This halt effectively freezes activity for
instructions in their F1, F2, and D1 phases. However, because the F1−D1
hardware and the D2−W hardware are decoupled, instructions that are in
their D2−W phases continue to execute.
- Wait states in the R1 phase. All D2−W activities of the pipeline freeze.
This is necessary because subsequent instructions can depend on the
data-read taking place. Instruction fetching continues until the instruction-
fetch queue is full or a wait-state request is received during an F1 phase.
- Wait states in the W phase. All D2−W activity in the pipeline freezes. This
is necessary because subsequent instructions may depend on the write
operation happening first. Instruction fetching continues until the instruc-
tion-fetch queue is full or a wait-state request is received during an F1
phase.
4.3.2 Instruction-Not-Available Condition
The D2 hardware requests an instruction from the instruction-fetch queue. If
a new instruction has been fetched and has completed its D1 phase, the
instruction is loaded into the instruction register for more decoding. However,
if a new instruction is not waiting in the queue, an instruction-not-available
condition exists. Activity in the F1−D1 hardware continues. However, the activ-
ity in the D2−W hardware ceases until a new instruction is available.
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