Freezes in Pipeline Activity
4-11Pipeline
One time that an instruction-not-available condition will occur is when the first
instruction after a discontinuity is at an odd address and has 32 bits. A
discontinuity is a break in sequential program flow, generally caused by a
branch, a call, a return, or an interrupt. When a discontinuity occurs, the
instruction-fetch queue is emptied, and the CPU branches to a specified
address. If the specified address is an odd address, a 16-bit fetch is performed
at the odd address, followed by 32-bit fetches at subsequent even addresses.
Thus, if the first instruction after a discontinuity is at an odd address and has
32 bits, two fetches are required to get the entire instruction. The D2−W hard-
ware ceases until the instruction is ready to enter the D2 phase.
To avoid the delay where possible, you can begin each block of code with one
or two (preferably two) 16-bit instructions:
FunctionA:
16-bit instruction ; First instruction
16-bit instruction ; Second instruction
32-bit instruction ; 32-bit instructions can start here
.
.
.
If you choose to use a 32-bit instruction as the first instruction of a function or
subroutine, you can prevent a pipeline delay only by making sure the instruc-
tion begins at an even address.
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