Memory Map
C.3 Memory Map
The major changes between the C2xLP and C28x memory maps are outlined
in this section. There are several differences between the C2xLP and C28x
memory maps. These improvements are due to the expanded architecture of
the C28x. The C28x CPU memory map ranges from 4G to 4M in data and pro-
gram memory, respectively. However, C28x CPU-based devices may not use
the entire memory range. See the device data sheet for the specific memory
range applicable to that device.
Vectors. On the C2xLP, only one vector table is present at address 0x0000.
These vectors were generally branch instructions to different interrupt service
routines. On the C28x, the vector table can be placed in two different locations
depending on the state of the VMAP input pin. On devices that do not pin out
the VMAP signal, it is tied internal to the device. Generally, vectors will be lo-
cated in non-volatile memory at 0x3FFFC0−0x3FFFFF. To take advantage of
relocatable vectors or fetching vectors from fast internal memory space, place
the vectors at address 0x000000−0x00003F. Often the C28x CPU interrupt
vectors are expanded using external hardware logic. In such cases, see the
related documents for the expanded vector map.
Memory space. On the C2xLP, the memory space for program, data, and I/O
space is each 64K words. On the C28x, the program memory space is 4M
words (22 address signals). The data memory space is 4G words (32 address
signals). The global space (32K) and I/O space (64K) is generally used for
C2xLP compatibility.
Program space. On the C2xLP CPU, program space could be mapped any-
where from (0x0−0xFFFF). With the extended address reach of the C28x (22
bits), the compatible region in program space for the C2xLP is
0x3F0000−0x3FFFF. Thus, any program memory on the C2xLP must be re-
mapped to this upper region on the C28x. When the processor accesses pro-
gram memory, the upper bits (bits 16−22) will be forced to all 1’s when C2xLP-
compatible instructions are used (See Appendix E).
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