Hardware Reset (RS)
3-25CPU Interrupts and Reset
Table 3−5. Registers After Reset (Continued)
Register Bit(s) Value After Reset Comments
ST1
‡
0: INTM 1 Maskable interrupts are
globally disabled. They
cannot be serviced unless
the C28x is in real-time
mode with the CPU
halted.
1: DBGM 1 Emulation accesses and
events are disabled.
2: PAGE0 0 PAGE0 stack addressing
mode is enabled. PAGE0
direct addressing mode is
disabled.
3: VMAP 1 The interrupt vectors are
mapped to program-
memory addresses
3FFFC0
16
−3FFFFF
16
.
4: SPA 0
5: LOOP 0
6: EALLOW 0 Access to emulation regis-
ters is disabled.
7: IDLESTAT 0
8: AMODE 0 C27x/C28x addressing
mode
9: OBJMODE 0 C27x object mode
10: Reserved 0
11: M0M1MAP 1
Note: The registers listed in this table are introduced in section 2.2, CPU Registers, on page
2-4.
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