CLRC Mode
6-72
CLRC Mode Clear Status Bits
SYNTAX OPTIONS OPCODE OBJMODE RPT CYC
CLRC mode 0010 1001 CCCC CCCC X − 1, 2
CLRC SXM 0010 1001 0000 0001 X − 1
CLRC OVM 0010 1001 0000 0010 X − 1
CLRC TC 0010 1001 0000 0100 X − 1
CLRC C 0010 1001 0000 1000 X − 1
CLRC INTM 0010 1001 0001 0000 X − 2
CLRC DBGM 0010 1001 0010 0000 X − 2
CLRC PAGE0 0010 1001 0100 0000 X − 1
CLRC VMAP 0010 1001 1000 0000 X − 1
Description Clear the specified status bits. The ”mode” operand is a mask value that
relates to the status bits in this way:
“Mode” bit Status Register Flag Cycles
0 ST0 SXM 1
1 ST0 OVM 1
2 ST0 TC 1
3 ST0 C 1
4 ST1 INTM 2
5 ST1 DBGM 2
6 ST1 PAGE0 1
7 ST1 VMAP 1
Note: The assembler will accept any number of flag names in any order.
Flags and
SXM
Any of the specified bits can be cleared by the instruction.
Modes
OVM
TC
C
INTM
DBGM
PAGE0
VMAP
Repeat This instruction is not repeatable. If this instruction follows the RPT
instruction, it resets the repeat counter (RPTC) and executes only once.
To Next Page
Loading...
Need help?
General
