CMPL ACC,loc32
6-80
CMPL ACC,loc32 Compare 32-bit Value
SYNTAX OPTIONS OPCODE OBJMODE RPT CYC
CMPL ACC,loc32 0000 1111 LLLL LLLL X − 1
Operands ACC Accumulator register
loc32 Addressing mode (see Chapter 5)
Description The content of the ACC register is compared with the 32-bit location pointed to
by the “loc32” addressing mode. The status flag bits are set according to the
result of (ACC − [loc32]). The ACC register and the contents of the location
pointed to by “loc32” are left unchanged:
Modify flags on (ACC − [loc32]);
Flags
and
Modes
N
If the result of the operation is negative, then N is set; otherwise it is cleared.
The CMPL instruction assumes infinite precision when it determines the sign
of the result. For example, consider the subtraction 0x8000 0000 − 0x0000
0001. If the precision were limited to 32 bits, the result would cause an
overflow to the positive number 0x7FFF FFFF and N would be cleared.
However, because the CMPL instruction assumes infinite precision, it would
set N to indicate that 0x8000 0000 − 0x0000 0001 actually results in a
negative number.
Z
The comparison is tested for a zero condition. The zero flag bit is set if the
operation (AX − [loc32]) = 0, otherwise it is cleared.
C
If the subtraction generates a borrow, C is cleared; otherwise C is set.
Repeat This instruction is not repeatable. If this instruction follows the RPT
instruction, it resets the repeat counter (RPTC) and executes only once.
Example
; Swap the contents of 32-bit VarA and VarB if VarB is higher:
MOVL ACC,@VarB ; ACC = VarB
MOVL P,@VarA ; P = VarA
CMPL ACC,@P ; Set flags on (VarB - VarA)
MOVL @VarA,ACC,HI ; VarA = ACC if higher
MOVL @P,ACC,HI ; P = ACC if higher
MOVL @VarA,P ; VarA = P
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