DMAC ACC:P,loc32,*XAR7/++
6-87
With some addressing mode combinations, you can get conflicting
references. In such cases, the C28x will give the “loc16/loc32” field
priority on changes to XAR7.
For example:
DMAC ACC:P,*−−XAR7,*XAR7++ ; −−XAR7 given priority
DMAC ACC:P,*XAR7++,*XAR7 ; *XAR7++ given priority
DMAC ACC:P,*XAR7,*XAR7++ ; *XAR7++ given priority
Flags and
Modes
Z
After the addition, the Z flag is set if the ACC value is zero, else Z is
cleared.
N
After the addition, the N flag is set if bit 31 of the ACC is 1, else N is cleared.
C
If the addition generates a carry of the ACC register, C is set; otherwise C
is cleared.
V
If an overflow of the ACC register occurs, V is set; otherwise V is not af-
fected.
OVC
If overflow mode is disabled; and if the operation generates a positive
overflow of the ACC register, then the counter is incremented. If overflow
mode is disabled; and if the operation generates a negative overflow of
the ACC register, then the counter is decremented.
OVM
If overflow mode bit is set; then the ACC value will saturate maximum pos-
itive (0x7FFFFFFF) or maximum negative (0x80000000) if the operation
overflowed. Note that OVM only affects the ACC operation.
PM
The value in the PM bits sets the shift mode for the output operation from
the product register. The PM mode affects both the ACC and P register
accumulates. If the product shift value is positive (logical left shift opera-
tion), then the low bits are zero filled. If the product shift value is negative
(arithmetic right shift operation), the upper bits are sign extended.
Repeat This instruction is repeatable. If the operation follows a RPT instruction,
then it will be executed N+1 times. The state of the Z, N, C and OVC flags
will reflect the final result in the ACC. The V flag will be set if an
intermediate overflow occurs in the ACC.
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