IMPYSL P,XT,loc32
6-107
IMPYSL P,XT,loc32 Signed 32-Bit Multiply (Low Half) and Subtract P
SYNTAX OPTIONS OPCODE OBJMODE RPT CYC
IMPYSL P,XT,loc32 0101 0110 0100 0011
0000 0000 LLLL LLLL
1 − 1
Operands P Product register
XT Multiplicand register
loc32 Addressing mode (see Chapter 5)
Description Subtract the unsigned content of the P register, ignoring the product shift
mode (PM), from the ACC register. Multiply the signed 32-bit content of the
XT register by the signed 32-bit content of the location pointed to by the
“loc32” addressing mode. The product shift mode (PM) then determines
which part of the lower 38 bits of the 64-bit result are stored in the P register:
ACC = ACC - unsigned P;
temp(37:0) = lower_38 bits(signed XT * signed [loc32]);
if( PM = +4 shift )
P(31:4) = temp(27:0), P(3:0) = 0;
if( PM = +1 shift )
P(31:1) = temp(30:0), P(0) = 0;
if( PM = 0 shift )
P(31:0) = temp(31:0);
if( PM = −1 shift )
P(31:0) = temp(32:1);
if( PM = −2 shift )
P(31:0) = temp(33:2);
if( PM = −3 shift )
P(31:0) = temp(34:3);
if( PM = −4 shift )
P(31:0) = temp(35:4);
if( PM = −5 shift )
P(31:0) = temp(36:5);
if( PM = −6 shift )
P(31:0) = temp(37:6);
Flags and
Modes
Z
After the subtraction, the Z flag is set if the ACC value is zero, else Z is
cleared.
N
After the subtraction, the N flag is set if bit 31 of the ACC is 1, else N is
cleared.
C
If the subtraction generates a borrow, C is cleared; otherwise C is set.
V
If an overflow occurs, V is set; otherwise V is not affected.
OVCU
The overflow counter is decremented when the subtraction operation gener-
ates an unsigned borrow. The OVM mode does not affect the OVCU counter.
PM
The value in the PM bits sets the shift mode that determines which portion of
the lower 38 bits of the 64-bit results are stored in the P register.
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