Texas Instruments TMS320C28x User Manual

INTR
6-114
INTR Emulate Hardware Interrupt
SYNTAX OPTIONS OPCODE OBJMODE RPT CYC
INTR INTx 0000 0000 0001 CCCC X − 8
INTR DLOGINT 0000 0000 0001 CCCC X − 8
INTR RTOSINT 0000 0000 0001 CCCC X − 8
INTR NMI 0111 0110 0001 0110 X − 8
INTR EMUINT 0111 0110 0001 1100 X − 8
Operands INTx Maskable CPU interrupt vector name, x = 1 to 14
DLO-
GINT
Maskable CPU datalogging interrupt
RTOSINT Maskable CPU real-time operating system interrupt
NMI Nonmaskable interrupt
EMUINT Maskable emulation interrupt
Description Emulate an interrupt. The INTR instruction transfers program control to
the interrupt service routine that corresponds to the vector specified by the
instruction. The INTR instruction is not affected by the INTM bit in status
register ST1. It is also not affected by enable bits in the interrupt enable
register (IER) or the debug interrupt enable register (DBGIER). Once the
INTR instruction reaches the decode 2 phase of the pipeline, hardware
interrupts cannot be serviced until the INTR instruction is finished
executing (until the interrupt service routine begins).
INTx
where x =
Interrupt
Vector
INTx
where x =
Interrupt
Vector
0 RESET 9 INT9
1 INT1 10 INT10
2 INT2 11 INT11
3 INT3 12 INT12
4 INT4 13 INT13
5 INT5 14 INT14
6 INT6
7 INT7
8 INT8

Texas Instruments TMS320C28x Specifications

General

Brand	Texas Instruments
Model	TMS320C28x
Category	Processor
Language	English