CPU Registers
2-15Central Processing Unit
software, the corresponding interrupt will be serviced if it is enabled. You en-
able or disable a maskable interrupt with its corresponding bit in the IER. The
DBGIER indicates the time-critical interrupts that will be serviced (if enabled)
while the DSP is in real-time emulation mode and the CPU is halted.
The C28x CPU interrupts and the interrupt-control registers are described in
detail in Chapter 3, Interrupts. Also, the IFR, IER, and DBGIER are included
in Appendix A, Register Quick Reference.
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