Status Register (ST0)
2-30
Table 2−8. Bits Affected by the C Bit (Continued)
Instruction Affect of or Affect on C
SUBBL ACC,loc32 ACC = ACC − ([loc32] + ~C)
C = 0 on borrow else C = 1
SUBCU ACC,loc16 for(ACC − [loc16]<<15)
C = 0 on borrow else C = 1
SUBCUL ACC,loc32 for(ACC<<1 + P(31) − [loc32])
C = 0 on borrow else C = 1
SUBL ACC,loc32 C = 0 on borrow else C = 1
SUBL loc32,ACC C = 0 on borrow else C = 1
SUBR loc16,AX C = 0 on borrow else C = 1
SUBRL loc32,ACC C = 0 on borrow else C = 1
SUBU ACC,loc16 C = 0 on borrow else C = 1
SUBUL ACC,loc32 C = 0 on borrow else C = 1
SUBUL P,loc32 C = 0 on borrow else C = 1
XB pma,COND C bit used as test condition
XCALL pma,COND C bit used as test condition
XMAC P,loc16,*(pma) C = 1 on carry else C = 0
XMACD P,loc16,*(pma) C = 1 on carry else C = 0
XRETC COND C bit used as test condition
TC
Bit 2
Test/control flag. This bit shows the result of a test performed by either the TBIT (test bit)
instruction or the NORM (normalize) instruction.
The TBIT instruction tests a specified bit. When TBIT is executed, the TC bit is set if the
tested bit is 1 or cleared if the tested bit is 0.
When a NORM instruction is executed, TC is modified as follows: If ACC holds 0, TC is set.
If ACC does not hold 0, the CPU calculates the exclusive-OR of ACC bits 31 and 30, and
then loads TC with the result.
This bit can be individually set and cleared by the SETC TC instruction and CLRC TC
instruction, respectively. At reset, TC is cleared.
Table 2−9 lists the instructions that affect the TC bit. See the instruction set in
Chapter 6 for a complete description of each instruction.
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