Status Register ST1
2-36
When the CPU services an interrupt, the current value of LOOP is saved on the stack
(when ST1 is saved on the stack), and then LOOP is cleared. Upon return from the in-
terrupt, LOOP is not restored from the stack.
SPA
Bits 4
Stack pointer alignment bit. SPA indicates whether the CPU has previously aligned
the stack pointer to an even address by the ASP instruction:
0 The stack pointer has not been aligned to an even address.
1 The stack pointer has been aligned to an even address.
When the ASP (align stack pointer) instruction is executed, if the stack pointer (SP)
points to an odd address, SP is incremented by 1 so that it points to an even address,
and SPA is set. If SP already points to an even address, SP is not changed, but SPA is
cleared. When the NASP (unalign stack pointer) instruction is executed, if SPA is 1, SP
is decremented by 1 and SPA is cleared. If SPA is 0, SP is not changed.
At reset, SPA is cleared.
VMAP
Bit 3
Vector map bit. VMAP determines whether the CPU interrupt vectors (including the
reset vector) are mapped to the lowest or highest addresses in program memory:
0 CPU interrupt vectors are mapped to the bottom of program memory, addresses
00 0000
16
−00 003F
16
.
1 CPU interrupt vectors are mapped to the top of program memory, addresses
3F FFC0
16
−3F FFFF
16
.
On C28x designs, the VMAP signal is tied high internally, forcing the VMAP bit to be set
high on a reset.
This bit can be individually set and cleared by the SETC VMAP instruction and
CLRC VMAP instruction, respectively.
PAGE0
Bit 2
PAGE0 addressing mode configuration bit. PAGE0 selects between two mutually-ex-
clusive addressing modes: PAGE0 direct addressing mode and PAGE0 stack addres-
sing mode. Selection of the modes is as follows:
0 PAGE0 stack addressing mode
1 PAGE0 direct addressing mode
Note: Illegal Instruction Trap
Setting PAGE0 = AMODE = 1 will generate an illegal instruction trap.
PAGE0 = 1 is included for compatibility with the C27x. the recommended operating
mode for C28x is PAGE0 = 0.
This bit can be individually set and cleared by the SETC PAGE0 instruction and
CLRC PAGE0 instruction, respectively. At reset, the PAGE0 bit is cleared (PAGE0 stack
addressing mode is selected).
For details about the above addressing modes, see Chapter 5, Addressing Modes.
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