G-5Glossary
D
D1 phase: See decode 1 (D1) phase.
D2 phase: See decode 2 (D2) phase.
data logging: Transferring one or more packets of data from CPU registers
or memory to an external host processor.
data log interrupt (DLOGINT): A maskable interrupt triggered by the on-
chip emulation logic when a data logging transfer has been completed.
data page: A 64-word portion of the total 4M words of data space. Each data
page has a specific start address and end address. See also data page
pointer (DP) and current data page.
data page pointer (DP): A 16-bit pointer that identifies which 64-word data
page is accessed in DP direct addressing mode. For example, for as long
as DP = 500, instructions that use DP direct addressing mode will ac-
cess data page 500.
data-/program-write data bus (DWDB): The bus that carries data during
writes to data space or program space.
data-read address bus (DRAB): The bus that carries addresses for reads
from data space.
data-read data bus (DRDB): The bus that carries data during reads from
data space.
data-write address bus (DWAB): The bus that carries addresses for writes
to data space.
DBGIER: See debug interrupt enable register (DBGIER).
DBGM bit: See debug enable mask (DBGM) bit.
DBGSTAT: See debug status register (DBGSTAT).
debug-and-test direct memory access (DT−DMA): An access of a regis-
ter or memory location to provide visibility to this location during debug-
ging. The access is performed with variable levels of intrusiveness by a
hardware DT-DMA mechanism inside the core.
debug enable mask (DBGM) bit: A bit in status register ST1 used to enable
(DBGM = 0) or disable (DBGM = 1) debug events such as analysis
breakpoints or debug-and-test direct memory accesses (DT-DMAs).
Glossary
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