G-11Glossary
interrupt flag bit: A bit in the interrupt flag register (IFR). If the interrupt flag
bit is 1, the corresponding interrupt has been requested by hardware and
is awaiting approval by the CPU.
interrupt flag register (IFR): The register that contains the interrupt flag bits
for the maskable interrupts. If a bit in the IFR is 1, the corresponding inter-
rupt has been requested by hardware and is awaiting approval by the
CPU.
interrupt global mask (INTM) bit: A bit in status register ST1 that globally
enables or disables the maskable interrupts. If an interrupt is enabled in
the interrupt enable register (IER) but not by the INTM bit, it is not ser-
viced. The only time this bit is ignored is when the CPU is in real-time
mode and is in the debug-halt state; in this situation, the interrupt must
be enabled in the IER and in the DBGIER (debug interrupt enable regis-
ter).
interrupt priority: See hardware interrupt priority.
interrupt request: A signal or instruction that requests the CPU to execute
a particular interrupt service routine. See also approve an interrupt re-
quest and service an interrupt.
interrupt service routine (ISR): A subroutine that is linked to a specific in-
terrupt by way of an interrupt vector.
interrupt vector: The start address of an interrupt service routine. After ap-
proving an interrupt request, the CPU fetches the interrupt vector from
your interrupt vector table and uses the vector to branch to the start of
the corresponding interrupt service routine.
interrupt vector location: The preset location in program memory where
an interrupt vector must reside.
interrupt vector table: The list of interrupt vectors you assign in program
memory.
INTM bit: See interrupt global mask (INTM) bit.
ISR: See interrupt service routine (ISR).
Glossary
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