Texas Instruments TMS320F2837 D Series - Peripheral Write-Read Protection

C28x CPU + FPU + VCU + TMU and CLA
TMS320F2837xD Microcontroller Workshop - Architecture Overview 1 - 9
Peripheral Write-Read Protection
Peripheral Write-Read Protection
 CPU pipeline protects W-R order for the same address

Write-Read protection mechanism protects W-R order
for different addresses

The following address ranges have Write-Read Protection:
 Block Protected Zone 1 (0x0000 4000 to 0x0000 7FFF)
 Block Protected Zone 2 (0x0004 0000 to 0x0005 FFFF)
Suppose you need to write to a peripheral register and
then read a different register for the same peripheral
(e.g., write to control, read from status register)?
Peripheral Frame 1
ePWM
, eCAP, eQEP, DAC, CMPSS, SDFM
Peripheral Frame 2
McBSP
, SPI, uPP, WD, XINT, SCI, I2C, ADC, X-BAR, GPIO
Peripheral Frame 2
USB, EMIF, CAN, IPC, System
Control
The peripheral write-read protection is a mechanism to protect the write-read order for peripherals
at different addresses. This works similar to the CPU pipeline protection of write-read order for
the same address.