Texas Instruments TMS320F2837 D Series Workshop Guide And Lab Manual

Control Law Accelerator (CLA)
9 - 4 TMS320F2837xD Microcontroller Workshop - Control Law Accelerator
CLA Block Diagram
CLA Block Diagram
MPERINT1-8
CLA_INT1-8
LVF, LUF
PIE
C28x
CPU
INT11
INT12
CLA
Control & Execution
Registers
CLA Program Bus
CLA Data Bus
Task Triggers
(Peripheral Interrupts)
Task1 Trigger
Task2 Trigger
Task3 Trigger
Task4 Trigger
Task5 Trigger
Task6 Trigger
Task7 Trigger
Task8 Trigger
Program
RAM
MSG RAMs
CPU to CLA
CLA to CPU
Data
RAM
ePWM
HRPWM
CMPSS
SDFM
Registers
eCAP
eQEP
DAC
Registers
SPI A/B/C
McBSPA/B
uPP
Registers
ADC Results
GPIO Data
CLA Memory and Register Access
CLA Memory and Register Access
 Contains CLA program code
 Mapped to the CPU at reset
 Initialized by the CPU
CLA Program Memory
 Used to pass data between
the CPU and CLA
 Always mapped to both
the CPU and CLA
Message RAMs
 Contains variables and coefficients
used by the CLA program code
 Mapped to the CPU at reset
 Initialized by CPU
CLA Data Memory
Peripheral Register Access
LS0 - LS5 RAM
Program
RAM
(2Kw each)
MSG RAMs
CPU to CLA
CLA to CPU
(128w/128w)
LS0 - LS5 RAM
Data
RAM
(2Kw each)
ePWM
HRPWM
CMPSS
SDFM
Registers
eCAP
eQEP
DAC
PF1
Registers
SPI A/B/C
McBSPA/B
uPP
PF2
 Provides direct access to peripherals
 Either the CLA or DMA can have
access to a PF, but not both
 CPUx.SECMSEL register selects CLA
or DMA per PF (default is CLA)
Note: CPU1.CLA1 has access to EMIF2 for data only
Registers
ADC Results
GPIO Data
The CLA has access to the LSx RAM blocks and each memory block can be configured to be
either dedicated to the CPU or shared between the CPU and CLA. After reset the memory block

Texas Instruments TMS320F2837 D Series Specifications

General

Brand	Texas Instruments
Model	TMS320F2837 D Series
Category	Microcontrollers
Language	English