Direct Memory Access (DMA)
8 - 10 TMS320F2837xD Microcontroller Workshop - Direct Memory Access
DMA Throughput
DMA Throughput
4 cycles/word
(5 for McBSP reads)
1 cycle delay to start each burst
1 cycle delay returning from CH1
high priority interrupt
32-bit transfer doubles throughput
(except McBSP, which supports 16-bit transfers only)
Example: 128 16-bit words from ADC to RAM
8 bursts * [(4 cycles/word * 16 words/burst) + 1] = 520 cycles
Example: 64 32-bit words from ADC to RAM
8 bursts * [(4 cycles/word * 8 words/burst) + 1] = 264 cycles
DMA vs. CPU Access Arbitration
DMA has priority over CPU
If a multi-cycle CPU access is already in
progress, DMA stalls until current CPU
access finishes
The DMA will interrupt back-to-back CPU
accesses
Can the CPU be locked out?
Generally No!
DMA is multi-cycle transfer; CPU will sneak
in an access when the DMA is accessing the
other end of the transfer (e.g. while DMA
accesses destination location, the CPU can
access the source location)
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