Interrupts
4 - 12 TMS320F2837xD Microcontroller Workshop - Reset and Interrupts
Interrupt Processing
Maskable Interrupt Processing
Conceptual Core Overview
A valid signal on a specific interrupt line causes the latch
to display a “1” in the appropriate bit
1
0
1
(IFR)
“Latch”
INT14
INT1
INT2
Core
Interrupt
F28x
Core
(INTM)
“Global Switch”
(IER)
“Switch”
If the individual and global switches are turned “on” the
interrupt reaches the core
By using a series of flag and enable registers, the CPU can be configured to service one interrupt
while others remain pending, or perhaps disabled when servicing certain critical tasks. When an
interrupt signal occurs on a core line, the interrupt flag register (IFR) for that core line is set. If the
appropriate interrupt enable register (IER) is enabled for that core line, and the interrupt global
mask (INTM) is enabled, the interrupt signal will propagate to the core. Once the interrupt service
routine (ISR) starts processing the interrupt, the INTM bit is disabled to prevent nested interrupts.
The IFR is then cleared and ready for the next interrupt signal. When the interrupt servicing is
completed, the INTM bit is automatically enabled, allowing the next interrupt to be serviced.
Notice that when the INTM bit is ‘0’, the “switch” is closed and enabled. When the bit is ‘1’, the
“switch” is open and disabled. The IER is managed by ORing and ANDing mask values. The
INTM bit in the status register is managed by using in-line assembly instructions.
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