DMA Trigger Source Selection Registers
Selects the Trigger Source for each DMA channel
Each channel can be triggered by up to 256 interrupt sources
Select ‘no peripheral’ if trigger is generated by software
Default value = 0x00
See “Peripheral Interrupt Trigger Sources” table on next slide
CH4
31 - 24 7 - 0
CH3 CH2 CH1
23 - 16 15 - 8
DmaClaSrcSelRegs.DMACHSRCSEL1
reserved
31 - 24 7 - 0
reserved CH6 CH5
23 - 16 15 - 8
DmaClaSrcSelRegs.DMACHSRCSEL2
Note: DMACHSRCSELLOCK register can be used to lock above registers (lock bit for each register)
Peripheral Interrupt Trigger Sources
0 No Peripheral 13 ADCCINT3 36 EPWM1SOCA 49 EPWM7SOCB 70 TINT2 109 SPITXDMAA
1 ADCAINT1 14 ADCCINT4 37 EPWM1SOCB 50 EPWM8SOCA 71 MXEVTA 110 SPIRXDMAA
2 ADCAINT2 15 ADCCEVT 38 EPWM2SOCA 51 EPWM8SOCB 72 MREVTA 111 SPITXDMAB
3 ADCAINT3 16 ADCDINT1 39 EPWM2SOCB 52 EPWM9SOCA 73 MXEVTB 112 SPIRXDMAB
4 ADCAINT4 17 ADCDINT2 40 EPWM3SOCA 53 EPWM9SOCB 74 MREVTB 113 SPITXDMAC
5 ADCAEVT 18 ADCDINT3 41 EPWM3SOCB 54 EPWM10SOCA 95 SD1FLT1 114 SPIRXDMAC
6 ADCBINT1 19 ADCDINT4 42 EPWM4SOCA 55 EPWM10SOCB 96 SD1FLT2 131 USBA_EPx_RX1
7 ADCBINT2 20 ADCDEVT 43 EPWM4SOCB 56 EPWM11SOCA 97 SD1FLT3 132 USBA_EPx_TX1
8 ADCBINT3 29 XINT1 44 EPWM5SOCA 57 EPWM11SOCB 98 SD1FLT4 133 USBA_EPx_RX2
9 ADCBINT4 30 XINT2 45 EPWM5SOCB 58 EPWM12SOCA 99 SD2FLT1 134 USBA_EPx_TX2
10 ADCBEVT 31 XINT3 46 EPWM6SOCA 59 EPWM12SOCB 100 SD2FLT2 135 USBA_EPx_RX3
11 ADCCINT1 32 XINT4 47 EPWM6SOCB 68 TINT0 101 SD2FLT3 136 USBA_EPx_TX3
12 ADCCINT2 33 XINT5 48 EPWM7SOCA 69 TINT1 102 SD2FLT4
// Set DMA Channel 2 to trigger on EPWM1SOCA
DmaClaSrcSelRegs.DMACHSRCSEL1.bit.CH2 = 36;
Note: values not shown in table are reserved