TMS320F2837xD Microcontroller Workshop - Control Law Accelerator 9 - 1
Control Law Accelerator
Introduction
This module explains the operation of the control law accelerator (CLA). The CLA is an
independent, fully programmable, 32-bit floating-point math processor. It executes algorithms
independently and in parallel with the CPU. This extends the capabilities of the C28x CPU by
adding parallel processing. The CLA has direct access to the ADC result registers. Additionally,
the CLA has access to all ePWM, high-resolution PWM, eCAP, eQEP, CMPSS, DAC, SDFM,
SPI, McBSP, uPP and GPIO data registers. This allows the CLA to read ADC samples “just-in-
time” and significantly reduces the ADC sample to output delay enabling faster system response
and higher frequency operation. The CLA responds to peripheral interrupts independently of the
CPU. Utilizing the CLA for time-critical tasks frees up the CPU to perform other system,
diagnostics, and communication functions concurrently.
Module Objectives
Module Objectives
Explain the purpose and operation of the
Control Law Accelerator (CLA)
Describe the CLA initialization procedure
Review the CLA registers, instruction set,
and programming flow
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