Lab 9: CLA Floating-Point FIR Filter
9 - 20 TMS320F2837xD Microcontroller Workshop - Control Law Accelerator
Setup CLA Initialization
During the CLA initialization, the CPU memory block RAMLS4 needs to be configured as CLA
program memory. This memory space contains the CLA Task routines. A one-time force of the
CLA Task 8 will be executed to clear the delay buffer. The CLA Task 1 has been configured to
run an FIR filter. The CLA needs to be configured to start Task 1 on the ADCAINT1 interrupt
trigger. The next section will setup the PIE interrupt for the CLA.
5. Open ClaTasks_C.cla and notice Task 1 has been configured to run an FIR filter.
Within this code the ADC result integer (i.e. the filter input) is being first converted to
floating-point, and then at the end the floating-point filter output is being converted back
to integer. Also, notice Task 8 is being used to initialize the filter delay line. The .cla
extension is recognized by the compiler as a CLA C file, and the compiler will generate
CLA specific code.
6. Edit Cla_9.c to implement the CLA operation as described in the objective for this lab
exercise. Set RAMLS0, RAMLS1, RAMLS2, and RAMLS4 memory blocks as shared
between the CPU and CLA. Configure the RAMLS4 memory block to be mapped to CLA
program memory space. Configure the RAMLS0, RAMLS1 and RAMLS2 memory blocks to
be mapped to CLA data memory space. Note that the RAMLS0 memory block will be
used for the CLA C compiler scratchpad. Set Task 1 peripheral interrupt source to
ADCAINT1 and set the other Task peripheral interrupt source inputs to “software” (i.e.
none). Enable CLA Task 1 interrupt. Enable the use of the IACK instruction to trigger a
task, and then enable Task 8 interrupt.
7. Open Main_9.c and add a line of code in main() to call the InitCla() function.
There are no passed parameters or return values. You just type
InitCla();
at the desired spot in main().
8. In Main_9.c comment out the line of code in main() that calls the InitDma() function.
The DMA is no longer being used. The CLA will directly access the ADC RESULT0
register.
Setup PIE Interrupt for CLA
Recall that ePWM2 is triggering the ADC at a 50 kHz rate. In the Control Peripherals lab exercise
(i.e. ePWM lab), the ADC generated an interrupt to the CPU, and the CPU read the ADC result
register in the ADC ISR. Then in the DMA lab exercise, the ADC instead triggered the DMA, and
the DMA generated an interrupt to the CPU, where the CPU read the ADC result register in the
DMA ISR. For this lab exercise, the ADC is instead triggering the CLA, and the CLA will directly
read the ADC result register and run a task implementing an FIR filter. The CLA will generate an
interrupt to the CPU, which will store the filtered results to a circular buffer implemented in the
CLA ISR.
9. Remember that in Adc.c we commented out the code used to enable the ADCA1
interrupt in PIE group 1. This is no longer being used. The CLA interrupt will be used
instead.
10. Using the “PIE Interrupt Assignment Table” find the location for the CLA Task 1 interrupt
“CLA1_1” and fill in the following information:
PIE group #: # within group:
This information will be used in the next step.
To Next Page
Loading...
Need help?
General
