Serial Communications Interface (SCI)
TMS320F2837xD Microcontroller Workshop - Communications 12 - 11
Idle-Line Wake-Up Mode
Idle time separates blocks of frames
Receiver wakes up when SCIRXD high for 10 or
more bit periods
Two transmit address methods
Deliberate software delay of 10 or more bits
Set TXWAKE bit to automatically leave exactly 11 idle bits
Last Data
ST
SPST Data
SCIRXD/
SCITXD
Block of Frames
SP SP
Last Data
ST Addr
SP
Idle
Period
10 bits
or greater
Idle
Period
10 bits
or greater
Address frame
follows 10 bit
or greater idle
1st data frame
SPST Addr
Idle periods
of less than
10 bits
Address-Bit Wake-Up Mode
All frames contain an extra address bit
Receiver wakes up when address bit detected
Automatic setting of Addr/Data bit in frame by setting
TXWAKE = 1 prior to writing address to SCITXBUF
Last Data
ST
ST Data
SCIRXD/
SCITXD
Block of Frames
SP SP
Last Data
ST Addr
SP
Idle Period
length of no
significance
First frame within
block is Address.
ADDR/DATA
bit set to 1
1st data frame
0 1 0
0
SPST Addr
1
SP
no additional
idle bits needed
beyond stop bits
The SCI interrupt logic generates interrupt flags when it receives or transmits a complete
character as determined by the SCI character length. This provides a convenient and efficient
way of timing and controlling the operation of the SCI transmitter and receiver. The interrupt flag
for the transmitter is TXRDY (SCICTL2.7), and for the receiver RXRDY (SCIRXST.6). TXRDY is
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