Reset and Boot Process
4 - 4 TMS320F2837xD Microcontroller Workshop - Reset and Interrupts
Dual-Core Boot Process
CPU1 starts execution from CPU1 boot
ROM while CPU2 is held in reset
CPU1 controls the boot process
CPU2 goes through its own boot process
under the control of CPU1 – except when
CPU2 is set to boot-to-flash
IPC registers are used to communicate
between CPU1 and CPU2 during the boot
process
During the F2837xD dual-core microcontroller booting, CPU1 controls the boot process and starts
execution from the CPU1 boot ROM while CPU2 is held in reset. CPU2 goes through its own
boot process under the control of CPU1, except when CPU2 is set to boot-to-flash. The IPC
registers are used to communicate between CPU1 and CPU2 during the boot process.
Additionally, the boot ROM contains the necessary boot loading routines to support peripheral
boot loading.