Analog Devices adsp-2100 User Manual

7 Host Interface Port
7 – 14
HSEL
HWR
HACK
ALE
HAD15–0
DATA
ADDRESS
HSEL
HRD
HACK
ALE
HAD15–0
ADDRESS DATA
Host Write Cycle
Host Read Cycle
selects a multiplexed read/write select with data strobe, and HMD1
selects separate address and data buses. The timing for the read cycle and
the write cycle is as follows:
1. The host asserts HRW and the address.
2. The host asserts H
DS and HSEL.
3. The ADSP-21xx returns HACK (and, for a read cycle, the data).
4. For a write cycle, the host asserts the data.
5. The host deasserts H
DS and HSEL.
6. The host deasserts HRW and the address (and, for a write cycle, the
data).
7. The ADSP-21xx deasserts H
ACK (and, for a read cycle, the data).
Figure 7.8 shows the HIP timing when HMD0=0 and HMD1=1. HMD0
selects separate read and write strobes, and HMD1 selects multiplexed
address and data buses. HD0-HD2 are used for the address. The timing
Figure 7.8 HIP Timing: Separate Strobes, Multiplexed Buses

Analog Devices adsp-2100 Specifications

General

Brand	Analog Devices
Model	adsp-2100
Category	Computer Hardware
Language	English