Deprag AST40-1 User Manual

24
Figure 6: Directory of the modules
7.6.1.3.1 Description of the transfer parameters (FB12)
Designation Type Data type Description
I_Addr1 INT
Input address from the hardware configuration
e.g. 256
I_Addr2 INT
Input address from the hardware configuration
e.g. 320
I_Addr3 INT
Input address from the hardware configuration
e.g. 384
I_Addr4 INT
Input address from the hardware configuration
e.g. 448
O_Addr1 INT
Output address from the hardware configuration
e.g. 256
O_Addr2 INT
Output address from the hardware configuration
e.g. 320
O_Addr3 INT
Output address from the hardware configuration
e.g. 384
O_Addr4 INT
Output address from the hardware configuration
e.g. 448
Control
IN
Structure
of UDT 21
Control signal data structure (see 7.6.1.3.2
Description of
the data structure of the control signals (UDT21)
)
State
Structure
of UDT 22
Status signal data structure (see 7.6.1.3.3
Description of
the data structure of the status signals (UDT22)
)
Data
OUT
Structure
of UDT 23
Data structure of the screwdriving data (see
7.6.1.3.5 Description of the data structure of the
screwdriving data (UDT23)
)
Table 10: Transfer parameters (FB12)

Deprag AST40-1 Specifications

General

Brand	Deprag
Model	AST40-1
Category	Controller
Language	English