Intel 855GME User Manual

4
Intel
®
855GME Chipset and Intel
®
6300ESB ICH Embedded Platform Design Guide
4.1.5.2 Topology 1B: Open Drain (OD) Signals Driven by the Intel
Pentium M/Celeron M Processor – FERR# and THERMTRIP# ............59
4.1.5.3 Topology 1C: Open Drain (OD) Signals Driven by the Intel
Pentium M/Celeron M Processor – PROCHOT#...................................60
4.1.5.4 Topology 2A: Open Drain (OD) Signals Driven by AND Gate–
PWRGOOD............................................................................................61
4.1.5.5 Topology 2B: CMOS Signals Driven by 6300ESB-LINT0/INTR,
LINT1/NMI, A20M#, IGNNE#, SLP#, SMI#, and STPCLK#...................62
4.1.5.6 Topology 3: CMOS Signals Driven by 6300ESB
to CPU and FWH – INIT# ......................................................................62
4.1.5.7 Voltage Translation Logic ......................................................................63
4.1.6 Pentium
®
M/Celeron
®
M Processor RESET# Signal.............................................64
4.1.6.1 Processor RESET# Routing Example ...................................................65
4.1.7 Pentium
®
M/Celeron
®
M Processor and Intel 855GME
Chipset GMCH (82855GME) Host Clock Signals..................................................66
4.1.8 Pentium
®
M/Celeron
®
M Processor GTLREF Layout and
Routing Recommendations ...................................................................................67
4.1.9 AGTL+ I/O Buffer Compensation...........................................................................69
4.1.9.1 Pentium
®
M/Celeron
®
M Processor AGTL+ I/O Buffer Compensation..69
4.1.10 Pentium
®
M/Celeron
®
M Processor System Bus Strapping..................................72
4.1.11 Pentium
®
M/Celeron
®
M Processor VCCSENSE/VSSSENSE
Design Recommendations.....................................................................................74
4.1.12 PLL Voltage Design for Low Voltage Intel
®
Pentium
®
M
Processors on 90 nm process with 2 MB L2 Cache..............................................74
4.2 Intel System Validation Debug Support..............................................................................75
4.2.1 ITP Support............................................................................................................75
4.2.1.1 Background/Justification........................................................................75
4.2.1.2 Implementation ......................................................................................75
4.2.2 Pentium
®
M/Celeron
®
M Processor Logic Analyzer Support (FSB LAI)................76
4.2.2.1 Background/Justification........................................................................76
4.2.2.2 Implementation ......................................................................................76
4.2.3 Intel
®
Pentium
®
M/Celeron
®
M Processor On-Die Logic
Analyzer Trigger (ODLAT) Support .......................................................................76
4.3 Onboard Debug Port Routing Guidelines ...........................................................................77
4.3.1 Recommended Onboard ITP700FLEX Implementation ........................................77
4.3.1.1 ITP Signal Routing Guidelines...............................................................77
4.3.1.2 ITP Signal Routing Example..................................................................81
4.3.1.3 ITP_CLK Routing to ITP700FLEX Connector........................................82
4.3.1.4 ITP700FLEX Design Guidelines for Production Systems......................83
4.3.2 Recommended ITP Interposer Debug Port Implementation..................................84
4.3.2.1 ITP_CLK Routing to ITP Interposer.......................................................84
4.3.2.2 ITP Interposer Design Guidelines for Production Systems....................85
4.3.3 Logic Analyzer Interface (LAI) ...............................................................................85
4.3.3.1 Mechanical Considerations....................................................................86
4.3.3.2 Electrical Considerations .......................................................................86
4.3.4 Processor Phase Lock Loop (PLL) Design Guidelines..........................................86
4.3.4.1 Processor PLL Power Delivery..............................................................86
4.3.4.2 Processor PLL Voltage Supply Power Sequencing...............................88
4.3.4.3 Processor PLL Decoupling Requirements.............................................88
4.3.5 Intel
®
Pentium
®
M/Celeron
®
M Processor Power Status Indicator (PSI#) Signal .89
4.3.6 Thermal Power Dissipation....................................................................................89
4.4 Intel
®
Pentium
®
M/Celeron
®
M Processor Decoupling Recommendations........................90

Intel 855GME Specifications

General

Brand	Intel
Model	855GME
Category	Computer Hardware
Language	English