Motorola MPC823e - Page 10

TABLE OF CONTENTS (Continued)
Paragraph Page
Number Title Number
viii MPC823e REFERENCE MANUAL MOTOROLA
11.6.1.7 MMU Data Real Page Number Register ....................11-26
11.6.1.8 MMU Instruction Access Protection Register .............11-31
11.6.1.9 MMU Data Access Protection Register ......................11-32
11.6.1.10 MMU Instruction Tablewalk Control Register .............11-33
11.6.1.11 MMU Data Tablewalk Control Register ......................11-34
11.6.1.12 MMU Tablewalk Base Register ..................................11-36
11.6.1.13 MMU Tablewalk Special Register ...............................11-37
11.6.2 MMU Data Content-Addressable Registers ...........................11-37
11.6.2.1 MMU Data CAM Entry Read Register ........................11-38
11.6.2.2 MMU Data RAM Entry Read Register 0 .....................11-39
11.6.2.3 MMU Data RAM Entry Read Register 1 .....................11-41
11.6.3 MMU Instruction Content-Addressable Registers ..................11-43
11.6.3.1 MMU Instruction CAM Entry Read Register ...............11-43
11.6.3.2 MMU Instruction RAM Entry Read Register 0 ............11-45
11.6.3.3 MMU Instruction RAM Entry Read Register 1 ............11-46
11.7 Interrupts ...........................................................................................11-47
11.7.1 Implementation-Specific Instruction TLB Miss .......................11-47
11.7.2 Implementation-Specific Data TLB Miss ................................11-47
11.7.3 Implementation-Specific Instruction TLB Error .......................11-48
11.7.4 Implementation-Specific Data TLB Error ................................11-48
11.8 Manipulating the Translation Lookaside Buffer .................................11-49
11.8.1 Reloading the Translation Lookaside Buffer ..........................11-49
11.8.1.1 Translation Reload Examples .....................................11-50
11.8.2 Controlling the TLB Replacement Counter ............................11-51
11.8.3 Invalidating the Translation Lookaside Buffer ........................11-51
11.8.4 Loading the Reserved TLB Entries ........................................11-51
11.9 Requirements For Accessing The Memory Management Unit
Control Registers ..............................................................................11-52
Section 12
System Interface Unit
12.1 Features ..............................................................................................12-2
12.2 System Configuration and Protection .................................................12-2
12.3 Interrupt Configuration ........................................................................12-5
12.3.1 The Interrupt Structure .............................................................12-5
12.3.2 Priority of the Interrupt Sources ...............................................12-6
12.3.3 Programming the Interrupt Controller .......................................12-7
12.3.3.1 SIU Interrupt Pending Register .....................................12-7
12.3.3.2 SIU Interrupt Mask Register .........................................12-8
12.3.3.3 SIU Interrupt Edge/Level Register ................................12-9
12.3.3.4 SIU Interrupt Vector Register .....................................12-10