Motorola MPC823e - Control Registers

The PowerPC Core
6-16 MPC823e REFERENCE MANUAL MOTOROLA
CORE
6
6.4.1 Control Registers
The following tables describe the core control registers, also known as special-purpose
registers, implemented within the MPC823e.
Table 6-7. Standard Special-Purpose Registers
SPR REGISTER
NAME
PRIVILEGED SERIALIZE ACCESS
DECIMAL SPR
5:9
SPR
0:4
1 00000 00001 XER No Write: Full Sync
Read: Sync Relative to Load/
Store Operations
8 00000 01000 LR No No
9 00000 01001 CTR No No
18 00000 10010 DSISR Yes Write: Full Sync
Read: Sync Relative to Load/
Store Operations
19 00000 10011 DAR Yes Write: Full Sync
Read: Sync Relative to Load/
Store Operations
22 00000 10110 DEC Yes Write
26 00000 11010 SRR0 Yes Write
27 00000 11011 SRR1 Yes Write
272 01000 10000 SPRG0 Yes Write
273 01000 10001 SPRG1 Yes Write
274 01000 10010 SPRG2 Yes Write
275 01000 10011 SPRG3 Yes Write
287 01000 11111 PVR Yes No (Read-Only Register)
Table 6-8. Standard Timebase Register Mapping
SPR REGISTER
NAME
PRIVILEGED SERIALIZE ACCESS
DECIMAL SPR
5:9
SPR
0:4
268 01000 01100
TBL Read
2
No Write - As a Store
269 01000 01101
TBU Read
2
No Write - As a Store
284 01000 11100
TBL Write
3
Yes Write - As a Store
285 01000 11101
TBU Write
3
Yes Write - As a Store
NOTES: 1. Extended opcode for mftb, 371 rather then 339.
2. Any write (mtspr) to this address results in an implementation-dependent software emulation interrupt.
3. Any read (mftb) to this address results in an implementation-dependent software emulation interrupt.