PowerPC Architecture Compliance
MOTOROLA MPC823e REFERENCE MANUAL 7-15
PPC ARCHITECTURE
7
COMPLIANCE
SRR1—Save/Restore Register 1
1–4 Set to 0.
10–15 Set to 0.
Other Loaded from bits 16-31 of the MSR. In the current implementation, Bit 30 of
the SRR1 is never cleared, except by loading a zero value from MSR
RI
.
MSR—Machine State Register
IP No change.
ME No change.
LE Bits are copied from the ILE.
Other Set to 0.
DSISR—Data/Storage Interrupt Status Register
0 Set to 0.
1 Set to 1 if the translation of an attempted access is not found in the translation
tables. Otherwise, set to 0.
2–3 Set to 0.
4 Set to 1 if the storage access is not permitted by the protection mechanism;
otherwise set to 0.
5 Set to 0.
6 Set to 1 for a store operation and to 0 for a load operation.
7–31 Set to 0.
DAR—Data Address Register
Set to the effective address of the data access that caused the interrupt.
Some instruction TLB registers are set to the values described in
Section 11 Memory Management Unit. Execution resumes at offset x’01400’ from the
base address indicated by MSR
IP
.
7.3.7.3.15 Implementation-Specific Debug Register. An implementation-specific debug
interrupt occurs as a result of one of the following conditions:
• When there is an internal breakpoint match (for more details, refer to
Section 20.3 Generating Watchpoints And Breakpoints).
• When a peripheral breakpoint request is presented to the interrupt mechanism.
• When the development port request is presented to the interrupt mechanism. Refer to
Section 20 Development Capabilities and Interface for details on how to generate
the development port request.
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