PowerPC Architecture Compliance
7-16 MPC823e REFERENCE MANUAL MOTOROLA
PPC ARCHITECTURE
7
COMPLIANCE
The following registers are set:
SRR0—Save/Restore Register 0
For I-breakpoints, set to the effective address of the instruction that caused the interrupt. For
L-breakpoint, set to the effective address of the instruction following the instruction that
caused the interrupt. For development port maskable request or a peripheral breakpoint, set
to the effective address of the instruction that the processor would have executed next if no
interrupt conditions were present. If the development port request is asserted at reset, the
value of SRR0 is undefined.
SRR1—Save/Restore Register 1
1–4 Set to 0.
10–15 Set to 0.
Other Loaded from bits 16-31 of the MSR. In the current implementation, Bit 30 of
the SRR1 is never cleared, except by loading a zero value from MSR
RI
.
If the development port request is asserted at reset, the value of SRR1 is undefined.
MSR—Machine State Register
IP No change.
ME No change.
LE Bits are copied from the ILE.
Other Set to 0.
For L-bus breakpoint instances, the following registers are set to:
BAR—Breakpoint Address Register
Set to the effective address of the data access as computed by the instruction that caused
the interrupt.
DSISR—Data/Storage Interrupt Status Register
Do not change.
DAR—Data Address Register
Do not change.
The execution resumes from an address equal to the base indicated by the MSR
IP
and the
following offset.
• x’01D00’–For an instruction breakpoint match
• x’01C00’–For a data breakpoint match
• x’01E00’–For a development port maskable request or a peripheral breakpoint
• x’01F00’–For a development port nonmaskable request
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